Here is a suggested list to help guide discussions.

• individual layer thickness and how you want to define that thickness
• required thickness uniformity (wafer to wafer, within wafer)
• layer doping and its uniformity
• layer-to-layer or substrate to layer doping transition width
• thermal issues (root DT considerations)
• wet chemical cleaning requirements (particularly with patterned wafers)
• wafer diameter
• pattern distortion and washout

On the epi structure:

• Required thickness/composition uniformity
• Epi (poly) surface roughness requirement
• Ge ramp linearity
• Oxygen concentration limit
• Definitions of layer thickness, composition

General issues for HBT-type Structures:

• Selective vs. non-selective
• Nitride vs. oxide dielectric
• Polycrystalline or amorphous seed layer, or no seed layer (for non-selective)
• On non-selective, what poly to single crystal thickness ratio is desired?
• Effects of pre epi processing on dielectric/single crystal interface
• Thermal budget issues (relates to insitu removal of native oxide in windows)
• Required pre-epi processing, e.g., 'scratch' oxide removal, damage to features from overetch, etc. (in addition to 100:1 HF)
• Si buffer layer thickness or no buffer layer
• Addition of carbon to suppress boron diffusion
• Subsequent thermal budget issue